Explain why instructions and data can be stored together in memory.
Part I · Chapter 2 · Computer Fundamentals
Von Neumann Architecture
A visual lesson on how a stored-program computer connects the CPU, memory, input, and output—and how one instruction moves through the fetch–decode–execute cycle.
Input
keyboard · sensor
IN
CPU
Control Unit
ALU
registers coordinate each instruction
Memory
instructions + data
100LOAD 105
1057
Learning goals
What you should understand
By the end of the lesson, you should be able to explain the model, identify its components, and trace a simple instruction.
Identify the CPU, memory, input, output, and system buses.
Describe the roles of PC, MAR, MDR, CIR, and accumulator.
Trace the fetch, decode, and execute phases step by step.
Interactive diagram
Explore the architecture
Select a component or a bus to see its role in the computer system.
Input Unit
Supplies data and commands to the computer.
IN
Output Unit
Presents processed results to a user or another system.
OUT
Processor
CPU
Central Processing Unit
Fetches, decodes, and executes program instructions.
Control Unit (CU)
Coordinates timing, instruction decoding, and control signals.
Arithmetic Logic Unit (ALU)
Performs arithmetic, comparisons, and logical operations.
PC
MAR
MDR
CIR
ACC
FLAGS
Main Memory
Stores program instructions, input data, intermediate values, and results.
100LOAD 105
101ADD 106
102STORE 107
1057
1065
Central Processing Unit
The CPU controls program execution. Its control unit directs data movement, its ALU performs operations, and its registers hold values needed immediately.
Instruction-cycle simulator
Watch a program run
This simplified program calculates 7 + 5, stores the result, displays it, and stops. Use “Next step” to follow the CPU’s internal work.
Program and data in shared memoryAddress → content
| Address | Memory content | Type |
|---|
The same memory contains executable instructions at addresses 100–104 and data at addresses 105–107.
Fetch–decode–execute cycleStep 1 of 23
1. Fetch
2. Decode
3. Execute
Ready to begin
The Program Counter points to address 100, where the first instruction is stored.
PC · Program Counter100
MAR · Memory Address—
MDR · Memory Data—
CIR · Current Instruction—
ACC · Accumulator0
OUTPUT—
Important limitation
The Von Neumann bottleneck
The processor can operate very quickly, but instructions and data must repeatedly move between memory and the CPU through shared pathways.
Shared path can restrict throughput
When the CPU waits for an instruction or data value to arrive from memory, processing capacity is underused. Cache memory, wider buses, pipelining, and other architectural techniques help reduce this delay.
Von Neumann
Instructions and data share memory and buses.
Harvard
Instructions and data use separate memories or pathways.
Knowledge check
Five-question mini quiz
Select an answer, check it, and use the explanation to review the concept.
Choose one option, then select “Check answer.”
Score: 0/5
Lesson summary
Four ideas to remember
Instructions and data are stored as binary patterns in addressable memory locations.
The control unit, ALU, and registers cooperate to perform each instruction.
The CPU repeatedly fetches, decodes, and executes instructions until the program stops.
Address, data, and control buses connect the processor, memory, and input/output units.